【招聘结束】 Digital IC Design Verification EngineerID:39687

该职位的招聘已结束

4,500 MYR ~ 8,000 MYRKulim3个月以上前

概述

  • 薪资

    4,500 MYR ~ 8,000 MYR

  • 产业类别

    Manufacturing(Electronics/Semiconductors)

  • 工作内容

    * Strong background in ASIC design flow (RTL to GDS)
    * Strong coding skill in VERILOG/VHDL for synthesis able RTL and behavioral modeling, system verilog, Verilog - AMS is a plus.
    * Working experience in FPGA design, debugging.
    * Strong verification skills using SVA, UVM, OVM, DFT
    * Scripting language experience a plus (perl, makefile,bash,tcl,...etc)
    * Familiar with C coding, MATLAB is a plus
    * Familiar with ECO Flow, FMEA is a plus
    * Able to work independently and in team environment. Able to lead projects/team.

资格

  • 应征条件

    Language : English
    Education Background : Graduates from Electrical Engineering or Computer Science
    Experience: Minimum 5 Years experience
    Required Skills:
    - Strong background in ASIC design methodology and EDA tools for simulation and verification, synthesis, P&R, formal verification and static timing analysis.
    - Strong coding skill in verilog/VHDL RTL and behavioral code, experience with system verilog will be plus.
    - Experience with design trough complete from RTL and GDS flow and familiar with ECO flow.
    - Familiar with Linux Environment (including shell scripting and linux gnu tools). Scripting language experience a plus ( perl, ruby, tcl, etc)
    - Have successfully defined, developed and implemented digital logic. Familiarity with Cadence/ Mentor Graphics/ Synopsys environment is a plus. Working experience in FPGA design and development software.
    - Highly self-motivated and excellent in problem solving and time management skills.
    Age: 28 - 45
    Gender : Open
    Others :Ability to travel is a plus. Able to work independently and in team environment.

  • 英文

    -

  • 其他语言

    Malay, Hindi, Mandarin

附加信息