33 Jobs: Job Vacancies for Bandar Sunway/Puchong Area
Sales Engineer ID:59740
4,000 MYR ~ 7,000 MYRBandar Sunway/PuchongJob Description
【Key Responsibilities】• Technical Consultation: To provide solutions based on clients requirements and recommend appropriate Commercial Hot Water Heater System and Kitchen Appliances.• Proposals & Design: Prepare technical proposals, including costing, and equipment specifications that comply with client’s need.• Product Demonstrations: Deliver technical presentations and live equipment demonstrations to solves customer’s need.• Sales Support: Manage technical aspects responses and assist in closing deals by resolving technical objections.• Post-Sales Support: Provide technical training for client staff and troubleshooting installed hot water heater system and kitchen equipment.
Benefit
• Petrol - MYR 0.6 / per km
• Toll & Parking - claim as per receipt ( during working hour only)
• Medical Allowance - MYR 500 / per year (dental / medical)
• Mobile Phone Allowance - MYR 200 / per month
• Entertainment Claim - MYR 200 / per month
• Travel Allowance - MYR 50 / per day (domestic) & MYR 100 / per day (international) (only for business trip)
• Accommodation - MYR 150 / per night (domestic) & MYR 420 / per day (international) (only for business trip)
• Group insurance Converge - Medical & hospitalisation
•EPF & Socso
• Annual Leave - as per below
Less than 2 years：12 days
Between 2 to 5 Years：17 days
More than 5 years：21 daysSenior/Staff Design for Testability (DFT) EngineerID:59731
8,000 MYR ~ 15,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking an experienced and strategic Senior or Staff DFT Design Engineer to join our team and in support the company’s ASIC design and IP development initiatives in the area of Design for Testability (DFT) design and verification. The candidate will play a key role in leading the planning and execution of various DFT features implementation and verification.Key Responsibilities:• DFT microarchitecture planning, DFT rtl generation/integration and verification of various DFT feature.• Memory BIST design implementation and verification for IP and ASIC projects.o Mbist logic insertion, integration and verification.o Mbist collateral generations including mbist pattern and timing constraint.• Scan design implementation and verification for IP and custom ASIC.o Scan controller generation (clock/reset control, test compression) implementation and scan chain stitchingo ATPG pattern generations and GLS simulation to verify the scan design.o Scan collaterals generation including scan constraint, scan timing closure, ATPG pattern debug etc.• JTAG/Boundary Scan design implementation and verificationo Tap controller design and verificationo Boundary scan chain implementation at IP and soc level, bscan verification and bsdl generation.• Post silicon debug and test pattern bring up supports to enable silicon power on activities and high-volume manufacturing testing.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior/Staff Digital Design EngineerID:59719
20,000 MYR ~ 25,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
This role will be responsible for architecting, designing, and verifying complex digital IPs and subsystems for SoCs or ASIC/FPGA-based products. As a senior role, it requires to work closely with system architects, verification, and physical design teams to deliver high-performance, power-efficient, and functionally correct RTL implementations. Overall, the responsibilities cover wider scope encompassing from IP to subsystem level and SOC level global issues.Key ResponsibilitiesArchitect with system engineers to perform:-• Define IP specifications, architecture & test concept.• Specify correct implementation of RTL design and verify digital circuits to deliver high performance, low power, and efficient implementation.• Conduct design reviews and support in documentation.• Support verification engineer to define verification test items.• Support in the roadmap formulation for the sensor IPs.• Support view generation engineers to verify the correctness of the Ips views.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSenior Staff Advanced Package & Board TeamID:59718
15,000 MYR ~ 30,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
The Senior Staff Advanced Package & Board Team will lead the design, development, and implementation of advanced IC packaging and board-level solutions that enable high-performance, cost-effective, and reliable silicon products. This role requires strong technical leadership across multiple engineering domains — including substrate/interposer design, board design, SI/PI/thermal analysis, and manufacturing interface — while driving cross-functional collaboration with silicon design, system architecture, and OSAT/EMS partners.The successful candidate will define and execute the company’s packaging and board technology roadmap to support next-generation chiplet-based architectures, 2.5D/3D integration, and heterogeneous systems.Key Responsibilities1. Leadership & Strategy• Lead the Advanced Package & Board Design Team, including substrate, interposer, and PCB design engineers.• Define and execute packaging and board technology strategy aligned with company silicon product roadmap.• Establish design and verification methodologies for advanced packaging (e.g., 2.5D, fan-out, chiplet integration).• Drive innovation in thermal management, signal integrity, and power delivery optimization.2. Technical Execution• Oversee design and validation of interposers, substrates, and system boards from concept to production release.• Guide integration of chiplets, HBM, and passive components using state-of-the-art packaging technologies.• Ensure robust SI/PI, mechanical, and thermal analysis for design sign-off.• Collaborate with silicon design teams on bump assignment, die floorplanning, and package co-design.• Manage board-level design for system bring-up, test platforms, and reference designs.3. Supplier & Ecosystem Management• Engage and qualify OSATs, substrate vendors, and PCB manufacturers to ensure quality and yield.• Partner with EDA vendors to establish design automation flow and DRC verification.• Drive technology transfer and pilot runs with manufacturing partners.4. Project & People Management• Plan resources, schedules, and budgets to ensure timely delivery of packaging and board design projects.• Build and mentor a high-performing team with expertise across electrical, mechanical, and materials engineering.• Foster collaboration across silicon, test, reliability, and operations teams.
Benefit
- Annual Leave
- Medical Leave
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementClient Service ExecutiveID:59669
3,000 MYR ~ 5,000 MYRBandar Sunway/PuchongJob Description
■ JOB OVERVIEWWe are looking for a proactive and logical Client Service Executives to act as a trusted partner to our clients. In this role, your key focus will be approaching new clients, understanding their core business challenges, and leading digital marketing projects to solve them. You will be responsible for the end-to-end process: from conducting client hearings and briefing internal teams, to compiling proposals, presenting solutions, and managing project profitability.While this is fundamentally a client-facing and project management role, logical thinking and data analysis are essential tools you will use daily to identify issues, build persuasive, data-driven proposals, and guide client business to success.■ KEY RESPONSIBILITIES・Client Partnership & Business Development: ・ Approach new clients and conduct thorough hearings to understand their business challenges, target audience, and marketing goals. ・ Build and maintain strong relationships, acting as a collaborative partner dedicated to solving their business issues.・Proposal Creation & Presentation: ・ Translate client challenges into clear, actionable briefs for the creative and production teams ・ Compile comprehensive proposal materials by synthesizing team ideas and utilizing data analysis to back up your strategies. ・ Present ideas, strategic marketing plans, and logical conclusions effectively to clients.・Project & Financial Management: ・ Drive the execution of digital marketing projects (including websites, SNS operations, creative, and online ads) alongside internal teams. ・ Manage project financials, keeping a close eye on revenue, budgets, and profit margins to ensure healthy project P&L. ・ Oversee administrative tasks such as quotations, billing, and schedule management.・Data-Driven Problem Solving: ・ Utilize logical thinking and an evidence-based approach to uncover the root causes of client challenges and formulate effective, realistic solutions.
Benefit
・Salary = RM 4,000 ~ RM 5,500
・Annual leave 12 days/year, increase by years.
・Bonus: once a year
・Incentive: depends on company performance
・Company support parking fee or public transportation fee.
・Private insurance for medical care
・Social Security Contribution
・Education and training
・Overseas Business Travel (Thailand, Vietnam, Singapore)
・Company Trip (depends on company performance)
・Customized education environment by CourseraGenerative AI DesignerID:59650
4,000 MYR ~ 5,500 MYRSeri Petaling, Bandar Sunway/Puchong, Kota Damansara/Petaling JayaJob Description
About the RoleWe are seeking a forward-thinking Generative AI Designer to join our creative team. This role is at the intersection of traditional design excellence and cutting-edge artificial intelligence. You will be responsible for leveraging AI tools to accelerate content creation while maintaining the high aesthetic standards and brand consistency our clients expect.Key Responsibilities1. AI-Assisted Visual Design: Use tools like Nano Banana Pro, Stable Diffusion, Adobe Firefly, and DALL-E 3 to produce high-quality marketing images, social media graphics, product visualizations, and branding elements.2. Prompt Engineering: Research, test, and refine complex AI prompts to achieve specific visual outcomes. Manage parameters, seed controls, and iterative workflows to ensure on-brand results.3. Post-Production & Refinement: Polish and "humanize" AI-generated outputs using traditional tools (Adobe Photoshop, Illustrator, After Effects) to ensure technical accuracy and professional quality.4. Brand Stewardship: Ensure all visual content—whether AI-generated or manually created-adheres strictly to company brand guidelines and maintains a consistent visual identity.5. Innovation & Research: Stay at the forefront of the GenAI landscape. Propose and implement new AI tools and workflows to improve speed-to-market and output quality. 6. Creative Collaboration: Participate in brainstorming sessions with marketing teams to develop campaign concepts and maintain a curated portfolio of AI-assisted work for internal and external showcasing.
Benefit
- Annual Leave: 14 days
- Medical Leave: 14 days
- Parking allowance: RM100
- Medical and dental claims: RM2000/year
- Medical insurance
- Performance bonusSr Library Design EngineerID:59656
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Library Design Engineer to own the end-to-end development of a production-grade standard cell library on leading-edge process nodes. You will drive transistor-level design, multi-Vt cell topology, full characterization, and PPA validation delivering robust, sign-off-ready library views to downstream implementation flows. Seniority level to be determined by experience.Key Responsibilities• Design, simulate, and analyze standard cell circuits at transistor level, including combinational, sequential, clock, and physical utility cells across multiple Vt flavors (HVT/SVT/LVT/ULVT) and drive strengths.• Perform layout process-node-shift; guide layout clean-up effort and review for DRC/LVS compliance, EM/IR rules, and parasitic awareness at the cell level.• Define & execute characterization flow to generate complete library views & models, covering timing (NLDM/CCS/ECSM), power (dynamic, leakage, internal), noise, and variation-aware models (LVF/SOCV/POCV); ensure Liberty, LEF, and GDS consistency.• Define & execute QA regression to check library quality; validate cell robustness including noise margin, drive strength, X-propagation, and scan/DFT cell correctness; drive STA correlation using PrimeTime or Tempus to confirm model accuracy in real PD flows.• Lead standard cell library IP integration into Testchip, including Testchip circuit and test plan development; support hardware bring-up and debug.• Perform pre/post-silicon correlation & model/design optimization; drive root-cause analysis for first-silicon issues and implement yield/robustness improvements.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr eFUSE Design EngineerID:59655
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking an eFUSE Design Engineer to own the end-to-end development of production-grade eFUSE IP on leading-edge process nodes. You will drive eFUSE array architecture, circuit design, full simulation-based verification, collateral and view generation, and quality checks — delivering robust, sign-off-ready eFUSE IP to downstream SoC integration flows. Bitcell-level design knowledge is valued; direct bitcell design experience is a plus but not required. Seniority level to be determined by experience.Key Responsibilities• Design and architect the eFUSE array circuit, including sense amplifier, reference bias, programming current control, address decoder, column multiplexer, and repair logic; ensure correct functional operation across all PVT corners.• Develop and execute comprehensive simulation plans for the eFUSE macro, covering DC/AC characterization, programming/read margin analysis, retention, endurance, and reliability corner simulations (MC, Mismatch, Aging); validate against product specifications and foundry bitcell models.• Generate and validate all required IP deliverable views and collateral: timing models (Liberty .lib), physical abstracts (LEF/GDS), behavioral models (Verilog), datasheets, and application notes; ensure consistency across all views and compliance with delivery checklist.• Define and execute IP quality checks (QC) and quality assurance (QA) regression suites; run DRC/LVS/ERC/PEX sign-off on the eFUSE macro layout; conduct formal and simulation-based functional verification; ensure all sign-off criteria are met prior to IP release.• Collaborate with the foundry and PDK team on eFUSE bitcell characterization data, SPICE models, and process design rules; translate foundry bitcell specifications and reliability requirements into array-level design constraints.• Support Testchip integration of the eFUSE macro, including test circuit design, programming and read test plan development; assist in hardware bring-up, failure analysis, and silicon–to–simulation correlation.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr Analog Circuit Design Engineer (General Purpose I/O) (GPIO)ID:59654
8,000 MYR ~ 16,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in GPIO (General Purpose I/O) design as described below. Seniority level to be determined by experience.Key Responsibilities• Own GPIO IP architecture/specs: bidirectional I/O, mixed-voltage/failsafe tolerance, programmable drive strength & slew-rate control, Schmitt-trigger inputs, pull-up/pull-down, bus-keeper/retention, and pad-ring support cells (supply, corner, filler, terminator/diode-breaker, cut cells).• Design and implement transistor-level GPIO circuits: input receiver, output driver, level shifters, predrivers, reference/compensation sub-blocks, analog test hooks.• Ensure robust reliability and quality signoff for I/O cells and rings (ESD, latch-up, EM/IR, aging, overstress, noise immunity and ground-bounce/SSN considerations).• Run comprehensive simulations and verification (PVT corners/Monte Carlo, pre- and post-layout, worst-case timing and functional modes) and drive design reviews with clear documentation.• Develop and release collateral for IP enablement: datasheets, integration guidelines, characterization reports, and models (SPICE/Verilog-A, and IBIS where applicable).• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.• Perform SI/PI and I/O behavior checks at the package/board interface level; support IBIS-based signoff and customer debug as needed.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly IncrementSr Analog Circuit Design Engineer (Clocking)ID:59653
10,000 MYR ~ 22,000 MYRBayan Lepas, Bayan Baru, Bandar Sunway/PuchongJob Description
We are seeking a Circuit/Analog Design Engineer to develop high-performance analog/mixed-signal IPs from architecture through tapeout and silicon bring-up. The candidate should have specialized expertise in Clocking as described below. Seniority level to be determined by experience.Key Responsibilities• Design and debug PLL/DLL architectures and circuits (integer/fractional-N; analog or digital-assisted).• Oscillators: LC or ring-oscillator (RO) VCO/DCO, frequency synthesis, phase noise/jitter analysis and budgeting.• Delay lines, measurement/ruler circuitry, phase interpolators, and calibration/trim techniques.• DCC/DCM/DCA, clock tree/distribution, and clock management units; low-jitter clock generation and distribution networks.• Own end-to-end block/IP delivery: architecture studies, specification, transistor-level design, simulation, post-layout sign-off, and silicon bring-up/characterization.• Behavioral modeling (e.g., Verilog-A/SystemVerilog) to explore loop dynamics, spur/jitter mitigation and system interactions.• Build verification test benches; validate performance across PVT corners, mismatch/Monte Carlo (as applicable), and post-extraction parasitics.• Work closely with layout/mask designers: floorplanning guidance, layout reviews, and ensuring LVS/DRC clean implementation and parasitic awareness.• Meet quality and reliability requirements (e.g., EM/IR, aging/overstress); contribute to robust design methodology and sign-off checklists.• Support IP integration on to Testchip as well as post-silicon evaluation including correlation with simulation and root-cause analysis for first-silicon bring-up.
Benefit
- Annual Leave 14 days
- Medical Leave 14 days
- Medical Insurance
- Dental/Optical RM500/year
- Outpatient RM1000/year
- Performance Bonus
- Yearly Increment
